Jianping Hu
Ningbo University

Published : 3 Documents
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LOW LEAKAGE CIRCUITS DESIGN WITH OPTIMIZED GATE-LENGTH BIASING Wu, Yangbo; Fan, Xiaohui; Ni, Haiyan; Hu, Jianping
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 4: April 2014
Publisher : Institute of Advanced Engineering and Science

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Abstract

With the technology process scaling, leakage power dissipation is becoming a growing number of percentage in total power dissipation. This study presents a new method in the gate-length biasing technique to achieve a cost-effective gate-length with a most benefit between leakage reduction and delay increasing. With the optimized gate-length, typical combinational and sequential circuits are realized and simulated using HSPICE with the BSIM4.6.4 predictive models at a 45nm COMS process. The results show that leakage currents of typical combinational circuits reduce more and delay increase less. Moreover, leakage currents of mirror adder and transmission gate adder decrease 13.9% and 8.90%, respectively; and leakage power of 4-bit binary counters using C2MOS D Flip-Flop and Transmission-Gate D Flip-Flop reduce 38.36% and 20.05%, with the frequency of 5M, respectively. Therefore, the optimized gate-length biasing technique is an attractive approach in low power circuits design. DOI : http://dx.doi.org/10.11591/telkomnika.v12i4.4791
A POWER-GATING SCHEME FOR MOS CURRENT MODE LOGIC CIRCUITS Zou, Kaiyu; Hu, Jianping
Indonesian Journal of Electrical Engineering and Computer Science Vol 11, No 10: October 2013
Publisher : Institute of Advanced Engineering and Science

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Abstract

MOS Current-Mode Logic (MCML) is widely used for high-speed circuits. However, the MCML circuits have large static power consumptions due to their constant operation currents. This paper presents a power-gating scheme for MCML circuits to reduce their static power dissipations in sleep mode. The PMOS transistors for linear load resistors of MCML circuits are used for power-gating switches. A power-gating control circuit consisting of NMOS and PMOS transistors is added for switching power-gating switches under the control of the sleep signal. The structure and operation of the proposed power-gating scheme are presented. In order to verify the correctness of the proposed power-gating scheme, several basic cells and a full-adder based on MCML circuits are realized. All the circuits are simulated with HSPICE at SMIC 130nm technology. The simulation results show that the power dissipations of the MCML circuits can be greatly reduced by shutting down their idle logic blocks. DOI: http://dx.doi.org/10.11591/telkomnika.v11i10.2877
POWER-GATING SCHEME AND MODELING OF NEAR-THRESHOLD ADIABATIC FLIP-FLOPS Zang, Fangfang; Hu, Jianping; Cheng, Wei
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 1: January 2014
Publisher : Institute of Advanced Engineering and Science

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Abstract

Technology scaling increases the density and performance of nanometer circuits, resulting in both large dynamic and leakage dissipations. This paper presents power-gating scheme, modeling, and optimization of adiabatic flip-flops operating on near-threshold regions to reduce both dynamic and leakage dissipations. The power-gated logic blocks are realized with complementary pass-transistor adiabatic logic with the dual threshold technique to reduce active leakage dissipations. The improved complementary pass-transistor adiabatic logic circuits are used as the two-phase power-gating switches to reduce the sleep leakage dissipations. The analytical model for power-gating adiabatic sequential circuits was constructed, and the energy overhead of the proposed power-gating scheme was analyzed in detail. Near-threshold computing for a power-gating adiabatic mode-10 counter was verified. The results show that the proposed power-gating technique is suitable for the adiabatic units operating on near-threshold regions. DOI : http://dx.doi.org/10.11591/telkomnika.v12i1.3378